arithmetic units造句
例句與造句
- the part of execution in which an operand or instruction is read from main stora ge and written into a control unit or arithmetic unit register
執(zhí)行過(guò)程中的一個(gè)階段所需的時(shí)間，在此期間，計(jì)算機(jī)從主存儲(chǔ)器中取出指令或操作數(shù)，并將其存入控制器或運(yùn)算器的寄存器中。 - in modern vlsi technology, hundreds of thousands of arithmetic units fit on a 1cm 2 chip . the challenge is supplying them with instructions and data . stream architecture is able to solve the problem well
在摩爾定律作用下，在單芯片上可集成的晶體管數(shù)快速增長(zhǎng)，單芯片擁有成百上千的運(yùn)算單元不再是問(wèn)題，關(guān)鍵是如何給如此多的alu提供足夠的指令和數(shù)據(jù)。 - 3-d graphics on mobile phones is quite similar to 3-d graphics on pc in years past . there is no hardware acceleration, and processor speeds are quite low, and there also is the lack of floating point arithmetic unit in mobile phones
因此論文從通用的部分開(kāi)始論述,然后明了移動(dòng)平臺(tái)的特征,并試圖解釋三維引擎的一般原理和設(shè)計(jì)一個(gè)具有粗適性的基于游戲的三維圖形引擎。 - 2 montoye r k, hokenek e, runyon s l . design of the ibm risc system 6000 floating-point execution unit . ibm journal of research and development, 1990, 34 : 59-71.3 oberman s . floating-point arithmetic unit including an efficient close data path
我們采用90納米cmos標(biāo)準(zhǔn)單元工藝以及synopsys自動(dòng)布局布線流程進(jìn)行實(shí)驗(yàn)，實(shí)驗(yàn)結(jié)果表明該算法在高性能雙通路結(jié)構(gòu)的浮點(diǎn)加減運(yùn)算中引入后，可以使得近路徑的運(yùn)算延遲整體降低10.2%，且算法本身沒(méi)有造成新的關(guān)鍵路徑。 - so, we must design multimedia application-oriented computer architecture to fit the data processing demand of video compressing programs, we analyzed the parallelism of two representative video compressing programs-opendivx and tml9, and drew a conclusion that it is effective to run video compressing application programs on the processor which uses parallel arithmetic units
相對(duì)于視頻壓縮應(yīng)用而言，普通計(jì)算機(jī)的處理能力大大落后于處理需求。因此，對(duì)于多媒體應(yīng)用，必須采用并行的方法來(lái)解決，但是不能簡(jiǎn)單地使用普通并行機(jī)，必須針對(duì)這部分應(yīng)用的特點(diǎn)，采用并行的思想來(lái)設(shè)計(jì)面向多媒體應(yīng)用的計(jì)算機(jī)體系結(jié)構(gòu)。 - It's difficult to find arithmetic units in a sentence. 用arithmetic units造句挺難的
- with turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components . the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2 . in chapter 3 we study the vlsi-- dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit
在工程設(shè)計(jì)方法及結(jié)構(gòu)化設(shè)計(jì)和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設(shè)計(jì)流程，討論了高層次綜合的核心如何從描述推出電路構(gòu)成的設(shè)計(jì)思路，針對(duì)不同目標(biāo)的設(shè)計(jì)技巧討論了采用hdl語(yǔ)言進(jìn)行邏輯系統(tǒng)設(shè)計(jì)的方法，給出了用vhdl語(yǔ)言進(jìn)行代碼設(shè)計(jì)時(shí)的規(guī)范和風(fēng)格，在面向soc的驗(yàn)證策略討論了動(dòng)態(tài)和靜態(tài)的驗(yàn)證技術(shù)，提出了進(jìn)行單獨(dú)模塊驗(yàn)證、芯片的全功能驗(yàn)證和系統(tǒng)軟硬件協(xié)同驗(yàn)證的整體策略。 - after that, it gives the measures of designing dsp's assembler as a part of the dsp's software development environment together with the c-compiler . moreover, this paper explores the method of design the floating-point arithmetic unit . referring to the ieee754-1985 standard for binary floating-point arithmetic, the algorithm and the behavior description of floating-point adder and multiplier is given, and the simulation and verification is shown at the end of this paper
此外，本文還對(duì)處理器的浮點(diǎn)運(yùn)算單元設(shè)計(jì)做了初步的研究，以ansiieee-754浮點(diǎn)數(shù)二進(jìn)制標(biāo)準(zhǔn)為參考，借鑒了經(jīng)典的定點(diǎn)加法器和乘法器的設(shè)計(jì)，嘗試性的給出了浮點(diǎn)加法單元和乘法單元的實(shí)現(xiàn)模型和行為級(jí)上的硬件描述，并對(duì)其進(jìn)行仿真和驗(yàn)證。